1. Field of The Invention
The present invention relates to a method for forming plugs of a semiconductor devices, and more particularly, to a mask for forming a landing plug contact hole to vertically expose an active region of a semiconductor substrate to a bit line or storage node contact, and a plug forming method using the same.
2. Description of the Related Art
Recently, as design rules for semiconductor devices become smaller and the semiconductor devices become integrated with higher density, the size of the memory cells is gradually decreasing.
Achieving such a high-density integration of semiconductor devices requires vast studies of novel materials associated with lithography, cell structure and wiring, and of physical property limits associated with insulation layers, etc. In addition, there exists a need to gradually decrease the critical dimension (CD) of a bit line or storage node contact.
FIG. 1 is a plan view illustrating a mask pattern for forming landing plug contact holes in accordance with the prior art.
Referring to FIG. 1, a semiconductor substrate includes device active regions 10 and device inactive regions 12. A plurality of lines, i.e. gate electrodes 14, are formed on the semiconductor substrate at a constant interval. In this case, the active regions 10 between the gate electrodes 14 form contact areas e and f to be connected with bit lines or storage node contacts. In the prior art, as shown in FIG. 1, I-shaped linear masks 16 are used to form landing plug contact holes to expose contact areas e and f of the active regions 10 to the bit lines or storage node contacts.
FIG. 2 is a vertical sectional view illustrating the arrangement of landing plugs, bit lines and storage node contacts embedded in inter-insulation layers in accordance with the prior art. Now, a prior art method for forming bit lines and storage node contacts based on landing plugs embedded in contact holes of an inter-insulation layer will be explained with reference to FIG. 2.
In the prior art method, first, each device active region 10 of the semiconductor substrate is etched in a shallow trench isolation (STI) manner to form an associated device in the active region 12 as a device isolation layer is embedded in the resultant trench. Then, a cell transistor, including the gate electrodes 14, is formed on the semiconductor substrate, and a first inter-insulation layer 18 is formed to cover the overall upper surface of the semiconductor substrate formed with the cell transistor. The first inter-insulation layer 18, for example, is formed of an undoped silicate glass (USG) layer, boro phospho silicate glass (BPSG) layer, or the like.
The first inter-insulation layer 18, supported on the bottom semiconductor substrate, is etched by means of the I-shaped linear masks 16, thereby forming contact holes to expose the contact areas e and f of the active regions 10 between the gate electrodes 14.
Then, the contact holes of the first inter-insulation layer 18 are gap-filled with doped poly-silicon to form a conductive layer, and the resultant conductive layer is flattened by means of chemical mechanical polishing (CMP), etc. In this way, the first inter-insulation layer 18 is provided with landing plugs 24 embedded in the contact holes to be vertically connected to the bit lines or storage node contacts.
Subsequently, a second inter-insulation layer 28 is deposited on the first inter-insulation layer 18, and is partially etched to form bit line contact holes (not-shown) for the interconnection of the semiconductor substrate and bit lines.
Thereby, each multi-layer bit line 26 is formed on an upper surface of the second inter-insulation layer 28 by, for example, stacking a barrier metallic layer 26a, a bit line metallic layer 26b and a hard mask 26c in sequence, and patterning the same. After completing formation of the bit line 26, a third inter-insulation layer 30 is deposited on the overall upper surface of the second inter-insulation layer 28 to cover the bit line 26. The third inter-insulation layer 30, for forming storage node contacts, is formed of a boro-phospho silicate glass (BPSG) layer, high density plasma (HDP) oxide layer, or the like.
The third inter-insulation layer 30 is partially etched to form contact holes to be connected with the landing plugs 24 located there below. Then, the contact holes of the third inter-insulation layer 30 are gap-filled with doped poly-silicon to form a conductive layer, and the resultant conductive layer is flattened by means of chemical mechanical polishing, or the like, thereby forming storage node contacts 32 in the third inter-insulation layer 30. The resultant upper portion is provided with a storage node etching stop layer 34 and a sacrificial insulation layer 36 in sequence. Here, the sacrificial insulation layer 36, for example, is formed of a silicon nitride layer, or silicon oxide layer.
Subsequently, both the storage node etching stop layer 34 and the sacrificial insulation layer 36 are partially etched to form storage node receiving openings. The storage node receiving openings are embedded with doped poly-silicon to form a conductive layer, and the resultant conductive layer is flattened by means of chemical mechanical polishing or other etching processes, thereby forming storage node electrodes 38.
One problem of the prior art semiconductor device configured as stated above is that, due to the etching slope, each landing plug 24, to vertically connect each active region with an associated bit line or storage node contact, has an insufficiently narrow critical dimension (CD) at the lower surface thereof in contact with the active region of the semiconductor substrate, although it has a wide critical dimension at its upper surface which is in contact with the second inter-insulation layer 28. As a result, as clearly explained in FIG. 2, if the active region 10 between both the adjacent inactive regions 12 has a width A, the landing plug 24 comes into contact with the active region 10 only over a width C, while a width B remains is in a non-contact state.
Another problem of the prior art is that, in the etching of landing plug contact holes using the prior art I-shaped linear masks, the contact holes associated with the bit lines are aligned linearly with the other contact holes associated with the storage node contacts, thereby causing only approximately 60% of the overall surface area of the contact holes to be exposed to the active regions. In this case, the contact holes for the bit lines occupy the remaining 40% of the area.
If the landing plug contact holes associated with the bit lines or storage node contacts are inaccurately etched to be exposed to the inactive regions of the semiconductor substrate, it inevitably results in defective contact between the active regions of the semiconductor substrate and the bit lines or storage node contacts, making it impossible to achieve a desired threshold voltage margin of a cell transistor and cause current leakage.